1. Field of the Invention
The present invention relates to methods for driving liquid crystal panels, and more particularly to a method for driving a ferroelectric liquid crystal panel (hereinafter referred to as FLC).
2. Description of the Related Art
FIG. 2 is a sectional view showing a general construction of a FLC panel. Two glass substrates 5a and 5b are located opposite to each other. On the surface of one of the glass substrates 5a are located in parallel to each other a plurality of transparent signal electrodes S formed of indium tin oxide (hereinafter abbreviated as ITO). The plurality of signal electrodes are coated with a transparent insulating film 6a formed of SiO.sub.2 or the like. On the surface of the other glass substrate 5b located opposite to the signal electrodes S are located in parallel to each other a plurality of transparent scanning electrodes L formed of ITO or the like in the direction of crossing at right angle with the signal electrodes S. The plurality of scanning electrodes L are coated with a transparent insulating film 6b. On each insulating film 6a and 6b are respectively formed transparent orientation films 7a and 7b formed of polyvinyl alcohol or the like (hereinafter abbreviated as PVA) subjected to rubbing treatment. Two glass substrates 5a and 5b are laminated to each other with a sealing agent 8 with an injection port retained on part thereof. After FLC 9 are introduced into a space sandwiched between orientation films 7a and 7b from the injection port with vacuum injection, the above injection port is sealed with a sealing agent 8. Two glass substrates 5a and 5b thus laminated to each other are sandwiched between two polarizing plates 10a and 10b located in such a manner that the polarizing axes thereof run at right angle to each other.
FIG. 3 is a plane view showing a general construction of a FLC display (hereinafter referred to as FLCD) 4 wherein a scanning side driving circuit 11 is connected to the scanning electrodes L of the FLC panel 1 whereas a signal side driving circuit 1 is connected to the signal electrodes S of the FLC panel 1. There is shown in FIG. 3, for simplicity, a display composed of 16 scanning electrodes L and 16 signal electrodes, or a FLCD 4 composed of 16.times.16 pixels. Each of the scanning electrodes L are classified by adding a subscript i (i=0 through F) whereas each of the signal electrodes are classified by adding a subscript j (j=o through F). In the foregoing passage a pixel formed in a portion formed by any scanning electrode Li and any signal electrode S.sub.j which runs perpendicular to each other is designated by symbol A.sub.ij.
The scanning side driving circuit 11 serves as a circuit for applying a voltage to the scanning electrodes L. The circuit 11 comprises an address decoder, a latch, and a analog switch array all not shown in the drawings. The circuit 11 applies a select voltage V.sub.c1 to a scanning electrode Li corresponding to a designated address A.sub.x. On the other hand, the signal side driving circuit 12 serves as a circuit for applying a voltage to the signal electrodes S. The circuit 12 comprises a shift register, a latch and an analog switch array not shown in the drawings. The input data DATA applies an active voltage V.sub.s1 to a signal electrode S corresponding to "1" whereas input data DATA applies a non-active voltage V.sub.so to a signal electrode S corresponding to "0".
A FLC molecule 101 carries a spontaneous polarization P.sub.s in the direction perpendicular to the longitudinal axis of the molecule as shown in FIG. 10(B). The molecule receives force proportional to the vector product of an electric field E and the spontaneous polarization, the electric field E being created by the potential difference between the scanning electrodes L and the signal electrodes S. The molecule travels on the surface of a cone 102 having an angle 20 where .theta. is the tilt angle of the FLC. The molecule 101 has two stable states 104 and 105 as shown in FIG. 10(A). The feature of the molecule 101 is that when it is moved by the electric field E to reach an axis 107 the molecule 101 assumes a stable state 104 whereas when it is moved by the electric field E to reach an axis 106 the molecule 101 assumes the stable state 105. In addition, the molecule 101 receives a resilient force that allows the molecule 101 to return to the original position even if it is moved by the electric field E. Then by setting one of the polarizing plates 10a and 10b to either the is 104 or the axis 105, a pixel composed of FLC molecules in one stable state exhibits a dark state whereas a pixel composed of molecules in another stable state exhibits a bright state. Incidentally, by setting one of the polarizing axis 104 or 105 either to the axis 10A or 10B, a fair display can be given even if the polarizing plates 10a and 10b are not necessarily allowed to run at right angle to each other.
As a method for driving a FLCD used so far is a combination of voltage waveforms shown in FIG. 11A and FIG. 11B (refer to Japanese Laid-Open Patent No. HEI 4 (1992)-134420).
Reference Numeral (1) in FIG. 11A designates a waveform of a select voltage V.sub.CA applied to a scanning electrode L.sub.i to rewrite a pixel A.sub.ij on the scanning electrodes to a dark display state. On the other hand, Reference Numeral (2) in FIG. 11A designates a waveform of a non-select voltage V.sub.CB applied to the other scanning electrodes L.sub.k (k=i) to prevent rewriting a display state of a pixel A.sub.kj on the scanning electrode. Reference Numeral (3) in FIG. 11A designates a waveform of a rewriting voltage V.sub.SC applied to a signal electrode S.sub.j to rewrite a display state of a pixel A.sub.ij to a dark display state. Reference Numeral (4) in FIG. 11A designates a holding voltage V.sub.SG applied to the signal electrode S.sub.j to prevent rewriting the display state of the pixel A.sub.ij on the scanning electrode L.sub.i to which the select voltage V.sub.CA is applied. Reference Numerals (5) through (8) in FIG. 11A designate a waveform of a, voltage actually applied to pixels. Out of them, the waveform shown by (5) in FIG. 11A is the voltage waveform A-C applied to a pixel A.sub.ij when the select voltage V.sub.CA is applied to the scanning electrode L.sub.i and the rewriting voltage V.sub.sc is applied to the signal electrode S.sub.j. The waveform shown by (6) in FIG. 11A is a voltage waveform A-G applied to the pixel A.sub.ij when the select voltage V.sub.CA is applied to the scanning electrode L.sub.i and the holding voltage V.sub.SG is applied to the signal electrode S.sub.j. The waveform shownby (7) in FIG. 11A is a voltage waveform B-C applied to the pixel A.sub.kj when the non-select voltage V.sub.CB is applied to the scanning electrode L.sub.k and the rewriting voltage V.sub.SC is applied to the signal electrode S.sub.j. The waveform shown by (8) in FIG. 11A is a voltage waveform B-G when the non-select voltage V.sub.CB is applied to the scanning electrode L.sub.k and the holding voltage V.sub.SG is applied to the signal electrode S.sub.j.
In addition, the waveform shown by (1) in FIG. 11B is a select voltage V.sub.CE applied to the scanning electrode L.sub.i to rewrite the display state of the pixel A.sub.ij to a bright display state. The waveform shown by (2) in FIG. 11B is a non-select voltage V.sub.CH applied to other scanning electrode L.sub.k (k=i) to prevent rewriting the display state of the pixel A.sub.kj on the scanning electrode. The waveform shown by (3) in FIG. 11B is a rewriting voltage V.sub.SD applied to the signal electrode S.sub.j to rewrite to a bright display state the display state of the pixel A.sub.ij on the scanning electrode L.sub.i to which the select voltage V.sub.CE is applied. The waveform shown by (4) in FIG. 11B is a holding voltage V.sub.SH applied to the signal electrode S.sub.j to prevent rewriting the display state of the pixel A.sub.ij on the scanning electrode L.sub.i to which the select voltage V.sub.CE is applied. The waveforms shown by (5) through (8) in FIG. 11B designates a waveform of a voltage actually applied to a pixel. Out of such waveforms, the waveform shown by (5) in FIG. 11B is a voltage waveform E-D applied to a pixel A.sub.ij when the select voltage V.sub.CE is applied to the scanning electrode L.sub.i and the rewriting voltage V.sub.SD is applied to the signal electrode S.sub.j. The voltage waveform shown by (6) in FIG. 11B is a voltage waveform E-H applied to a pixel when the select voltage V.sub.CE is applied to the scanning electrode L.sub.i and the holding voltage V.sub.SH is applied to the signal electrode S.sub.j. The waveform shown by (7) in FIG. 11B is a voltage waveform FD applied to the pixel when the non-select voltage VCF is applied to the scanning electrode L.sub.k and the rewriting voltage V.sub.SD is applied to the signal electrode S.sub.j. The waveform shown by (8) in FIG. 11B is a voltage waveform F-H applied to the pixel A.sub.ij when the non-select voltage V.sub.CF is applied to the scanning electrode L.sub.k and the non-select voltage V.sub.SF is applied to the scanning electrode L.sub.k and the holding voltage V.sub.SH is applied to the signal electrode S.sub.j.
The above method for driving FLCD panel detects the difference between a state currently displayed on the FLCD and a state that should be displayed on the FLCD in the subsequent step to make distinct the following three cases;
1) a case in which the pixel changes from a dark display state to a bright display state,
2) a case in which the pixel changes from a bright display state to a dark display state, and
3) a case in which the display of the pixel does not change.
In case 1), the voltage waveform A-G shown by (6) in FIG. 11A and the voltage waveform E-D shown by (5) in FIG. 11B are applied to the pixel when selecting the display state. In case 2) the voltage waveform A-C shown by (5) in FIG. 11A and the voltage waveform E-H shown by (6) in FIG. 11B are applied to pixels when selecting the display state. In case 3), the voltage waveform A-G shown by (6) in FIG. 1A and the voltage waveform E-H shown by (6) in FIG. 11B are applied to pixels when selecting the display state.
A display control device using this driving method is the display control device 13 shown in FIG. 12.
In this display device 13, data to be displayed in the FLCD is made of a digital RGB signal (attached with clocking) transmitted from a personal computer shown in FIG. 1 to a CRT display 3. This digital RGB signal comprises a horizontal synchronous signal HD that generates a cycle between one horizontal scanning section of image data to be output to the display 3 shown by (1) in FIG. 4 and by (4) in FIG. 4, one vertical synchronous signal VD, a display data Data that constitutes data of the image, and a clock CLK for transmitting data. Incidentally, referring to 3) in FIG. 4, display data Data is classified by adding subscripts in each one horizontal scanning section. On the other hand, referring to (5) in FIG. 4 each pixel is classified by adding a number to each pixel.
This digital signal carries data only for 8.times.8 pixels. However, the FLCD can display 16.times.16 pixels just because 16.times.16 pixels on the FLCD are hypothetically divided into four display parts; display part P.sub.0 comprising scanning electrodes L.sub.0 through L.sub.7 and signal electrodes S.sub.0 through S.sub.7, display part P.sub.1 comprising scanning electrodes L.sub.0 through L.sub.7 and signal electrodes S.sub.8 through S.sub.F, and display part P.sub.2 comprising scanning electrodes L.sub.8 through L.sub.F and signal electrodes S.sub.0 through S.sub.7, and a display part P.sub.3 comprising scanning electrodes L.sub.8 through L.sub.F and signal electrodes S.sub.8 through S.sub.8 through S.sub.F ; and data in the 0th horizontal scanning sections designates which display parts P.sub.0 through P.sub.3 data in the 1st to the 8th horizontal scanning sections correspond to.
In other words, referring to FIGS. 5 and 6, when the 3rd data in the 0th horizontal scanning section assume a "bright" state (data without slanted lines) and the 7th data also assume a "bright" state (corresponding to FIG. 5) data in the following 1st to 8th horizontal scanning section correspond to display part P.sub.0. When the 3rd data in the 0th horizontal scanning section assume a "bright" state and the 7th data assume a "dark" state (data with slanted line), data in the following 1st to 8th horizontal scanning section correspond to display part P.sub.1. When the 3rd data in the 0th horizontal scanning section assume a "dark" state and the 7th data assume a "bright" state (corresponding to FIG. 6), data in the following 1st to 8th horizontal scanning section correspond to display part P.sub.2. When the 3rd data in the 0th horizontal scanning section assume a "dark" state and when the 7th data assume a "dark" state, data in the following 1st to 8th horizontal scanning section correspond to display part P.sub.3.
The construction of the display control device 13 is shown in a block diagram in FIG. 12. At the outset, the digital RGB signal output from the personal computer 2 is received at an interface circuit 13 and the signal is distributed to an input control circuit 18 and a display memory circuit 15.
The display memory circuit 15 records "ABCD" data already described in the FLCD 4 and shown in FIG. 3. Entering "E" display data Data shown in FIG. 5 allows recording "EBCD" data shown in FIG. 7. Besides, data variation in the memory circuit 15 at this point is shown in FIG. 8 in every pixel. Data variation in the display memory circuit 15 is grouped together in every two pixels (when a variation occurs in one pixel, it is recognized as a variation in the whole group of pixels) to be output to a group memory circuit 16 and a identity/non-identity circuit 17 as a transition data IDF.
In the group memory circuit 16, scanning electrodes L.sub.0, L.sub.1 correspond to group G.sub.o, electrodes L.sub.2 and L.sub.3 to group G.sub.1 and so on,--and scanning electrodes L.sub.E, L.sub.F correspond to group G.sub.7. When one of the transition data IDF corresponding to the group thereof assumes "1" (indicating the presence of variation), the identification data GDF corresponding to the group assumes "1" (indicating the presence of variation). When all the transition data IDF corresponding to the group assumes "0" (indicating the absence of variation), the identification data GDF corresponding to the group remain unchanged. In addition, the identification data GDF corresponding to the transition data IDF is output to the identity/non-identity memory circuit 17 as group transition data IGDF.
The identity/non-identity memory circuit 17 records as one data item four pixels in the vertical and horizontal directions of electrodes. The logical product of data recorded in correspondence to the transition data IDF and the group transition data IGDF and the logical addition of the transition data IDF corresponding to the data are recorded in a summarized form as shown in FIG. 9 (When there is a variation in any of the logical addition of four pixels, the presence of transition is recorded).
The input control circuit 18 controls the above input behavior.
In addition, the output control circuit 19 outputs a group address OAG.sub.x through an address shift-over circuit 20 to a group memory circuit 16, and receives the corresponding identification data GDF as an output identification data OGDF. When the data assumes "1" (indicating the presence of variation), the scanning electrode corresponding to the group is to be driven for partial rewriting operation. When the data assumes "0" (indicating absence of variation), the output control circuit 19 receives the output identification data OGDF in the following group.
Data DA is entered to a driving control circuit 21 from the display memory circuit 15. From the group memory circuit 16 are entered data RGDF and DGDF to the driving control circuit 21. From the identity/non-identity circuit 17 is entered data DF. In addition, from the output control circuit 19 is entered an address OAC.sub.x through the address shift-over circuit 20. Upon receipt of this data, the driving control circuit 21 outputs an address signal A.sub.x for controlling the behavior of the FLCD 4, the display data DATA, transfer clock XCLK, a timing signal. YCLK, LP, and driving voltage V.sub.C0, V.sub.C1, V.sub.S0 and V.sub.S1.
FIGS. 13 and 14 are a timing chart for illustrating a concrete behavior of this display control device 13. Reference Numeral (1) in FIG. 13 and (1) in FIG. 14 designate a horizontal synchronous pulse HP, which assumes "0" (low level in the FIG. 13 and 14) in each one select period 4t.sub.0. Reference Numeral (3) in FIG. 13 and (3) in FIG. 14 designate a driving mode H/R. Numeric value "1" (a high level in FIG. 13 and FIG. 14) designates a partial rewriting operation driving whereas numeric value "0" (a low level in FIG. 13 and 14) designates an interlace driving. Consequently, after one scanning electrode is subjected to interlaced driving, two scanning electrodes are partially rewritten and driven. Reference Numeral (2) in FIG. 13 and (2) in FIG. 14 designate an address DAC.sub.0 which becomes effective when the driving mode H/R assumes "1" namely in the partial rewriting driving and which is used for classifying two scanning electrodes in the group. Reference Numeral (4) in FIG. 13 and (4) in FIG. 14 designate a voltage mode E/W for changing over a combination of voltage waveforms shown in FIG. 11A and a combination of voltage waveforms shown in FIG. 11B by combining with the driving mode H/R. Reference Numeral (5) in FIG. 13 and 5) in FIG. 14 designate an address RAC.sub.x showing a scanning electrode that becomes effective in the interlaced driving. The address RAC.sub.x is reflected in the address OAC.sub.x shown by (8) in; FIG. 13 and by (8) in FIG. 14 during time 0 to 4t.sub.0 and time 12t.sub.0 to 16t.sub.0. Reference Numeral (6) in FIG. 13 and 6) in FIG. 14 designate an address DAC.sub.x for inspecting whether or not there is any variation in the output identification data OGDF corresponding to each group. Reference Numeral (7) in FIG. 13 and (7) in FIG. 14 is reflected on an address OAG.sub.x output to the group memory circuit 16 through the address shift-over circuit 20. Reference Numeral (8) in FIG. 13 and (8) in FIG. 14 designate an address OAC.sub.x output to the display memory circuit 15, the identity/non-identity circuit 17 and a driving memory circuit 21. For example, after an address "2" is output for interlaced driving during 12t.sub.0 to 16t.sub.0, addresses "0" and "1" for partial rewriting driving are output.
The behavior of this display control device 13 will be detailed hereinbelow in conjunction with FIGS. 13 and 14. In time t=0 through 4t.sub.0, the output control circuit 19 and the address shift-over circuit 20 allows the display memory circuit 15 and the identity/non-identity circuit 17 to output display data DA and the transition data DF corresponding to the scanning electrode L.sub.0. The address shift-over circuit 20 outputs an address OAC="D" to the driving control circuit 21. The output control circuit 19 outputs the driving mode H/R="0" and the voltage mode E/W="1" to the driving control circuit 21. Additionally, the output control circuit 19 and the address shift-over circuit 20 confirms the output identification data OGDF in groups G.sub.4 through G.sub.6 of the group memory circuit 16.
In the meantime, the input control circuit 18 transforms record data in the display memory circuit 15 from the "ABCD" state shown in FIG. 3 into the "EBCD state. The record data in the identity/non-identity memory circuit 17 is all transformed from the state of no variation to the state with the presence of variation having slanted lines. The identification data GDF in the group memory circuit 16 is transformed from the state of no variation to the state with variation in groups G.sub.0 through G.sub.3. In the subsequent process, record data in the display memory circuit 15 is kept in the "EBCD" state shown in FIG. 7.
In time t=4t.sub.0 through 8t.sub.0, the output control circuit 19 and the address shift-over circuit 20 allows the display memory circuit 15 and the identity/non-identity memory circuit 17 to output the display data DA and the transition data DF to the driving control circuit 21. The address shift-over circuit 20 outputs an address OAC="A" to the driving control circuit 21. The output control circuit, 19 outputs a driving mode H/R="1" and a voltage mode E/W="1" to the driving control circuit 21. At the same time, the output control circuit 19 and the address shift-over circuit 20 confirms the output identification data OGDF of group G.sub.7 and G.sub.0 in the group memory circuit 16. Since data in group G.sub.0 shows the presence of variation, the confirmation of the output identification data OGDF is suspended. This helps to partially rewrite and drive scanning electrodes L.sub.0 and L.sub.1 corresponding to group G.sub.0.
In time t=8t.sub.0 to 12t.sub.0, the output control circuit 19 and the address shift-over circuit 20 allows the display memory circuit 15 and the identity/non-identity memory circuit 17 to output the display data DA corresponding to the scanning electrode L.sub.B and the transition data DF to the driving control circuit 21. The address shift-over circuit 20 outputs the address OAC="B" to the driving control circuit 21. The output control circuit 19 outputs the driving mode H/R="1" and the voltages mode E/W="1" to the driving control circuit 21.
In time t=12t.sub.0 to 16t.sub.0, the output control circuit 19 and the address shift-over circuit 20 allows the display memory circuit 15 and the identity/non-identity memory circuit 17 to output the display data DA corresponding to scanning electrode L.sub.2 and the transition data DF to the driving control circuit 21. The address shift-over circuit 20 outputs the address OAC="2" to the driving control circuit 21. The output control circuit 19 outputs the driving mode H/R="0" and the voltage mode E/W="0" to the driving control circuit 21. At the same time, the output control circuit 19 and the address shift-over circuit 20 output the identification data RGDF corresponding to group G.sub.1 and the identification data DGDF corresponding to group G.sub.0 from the group memory circuit 16. The identification data GDF is restored to the state of no variation.
In time t=16t.sub.0 to 20t.sub.0, the output control circuit 19 and the address shift-over circuit 20 allows the display memory circuit 15 and the identity/non-identity memory circuit 17 to output the display data DA corresponding to the scanning electrode L.sub.0 and the transition data DF to the driving control circuit 21. The address shift-over circuit 20 outputs the address OAC="0" to the driving control circuit 21. The output control circuit 19 outputs the driving mode H/R="1" and the voltage mode E/W="0" to the driving control circuit 21. At the same time, the output control circuit 19 and the address shift-over circuit 20 confirms the output identification data OGDF of group G.sub.1 in the group memory circuit 16. Since the data of group G.sub.1 shows the presence of variation, the confirmation of the output identification data OGDF is suspended at this point. This helps to partially rewrite and drive scanning electrodes L.sub.2 and L.sub.3 corresponding to group G.sub.1.
In time t=20t.sub.0 to 24t.sub.0, the output control circuit 19 and the address shift-over circuit 20 allows the display memory circuit 15 and the identity/non-identity circuit 17 to output the display data DA corresponding to the scanning electrode L.sub.1 and the transition data DF to the driving control circuit 21. The address shift-over circuit 20 outputs the address OAC="1" to the driving control circuit 21. The output control circuit 19 outputs the driving mode H/R="1" and the voltage mode E/W="0" to the driving control circuit 21.
In the foregoing operation the above behavior is repeated. FIG. 15 shows voltages applied to scanning electrodes L.sub.0, L.sub.1 and L.sub.2, signal electrodes S.sub.1, S.sub.2 and S.sub.5, and pixels A.sub.11, A.sub.21, A.sub.22 and A.sub.25 as a consequence of the repetition of the above behavior. Reference Numeral (1) in FIG. 15 designates a voltage waveform applied to the scanning electrode L.sub.0, (2) a voltage waveform applied to the scanning electrode L.sub.1, (3) a voltage waveform applied to the scanning electrode L.sub.2, which is subjected to the interlaced scanning by using a combination of the voltage waveform shown in FIG. 11(A) which is followed by partial rewriting and scanning of the scanning electrode L.sub.0 and partial rewriting and scanning of the scanning electrode L.sub.1. Then after the scanning electrode L.sub.2 is subjected to the interlaced scanning by using a combination of the voltage waveform shown by FIG. 11(B), the scanning electrode L.sub.0 is partially rewritten and scanned and then the scanning electrode L.sub.1 is partially rewritten and scanned. Reference Numeral (4) in FIG. 15 designates a voltage waveform applied-to the signal electrode S.sub.1, (5) a voltage waveform applied to the signal electrode S.sub.2, (6) a voltage waveform applied to the signal electrode S.sub.5. Consequently, to the pixel A.sub.11 is applied a voltage waveform shown by (7) in FIG. 15. To the pixel A.sub.21 is applied a voltage waveform shown by (8) in FIG. 15. To the pixel A.sub.22 is applied a voltage waveform shown by (9) in FIG. 15. To the pixel A.sub.25 is applied a voltage waveform shown by (10) in FIG. 15. In other words, to the pixel A.sub.11 shown by (7) in FIG. 15 are applied voltage waveforms A-C shown in FIG. 11(A) during the partial rewriting and scanning period to be maintained in a dark stable state. To the pixel A.sub.21 shown by (8) in FIG. 15 are applied voltage waveforms E-D shown in FIG. 11(B) during the interlaced scanning period to be maintained in the bright stable state.
Use of the above driving method as described in Japanese Laid-Open Patent No. HEI 4 (1992)-134420 prevents flickers from being detected resulting from a partial rewriting operation driving. With a favorable memory properties of the FLCD no flicker resulting from the interlaced scanning is detected. A display free from a limit in the display capacity can be obtained even with a liquid crystal material having a slow response rate.
However, use of a liquid crystal materials having a slow response rate slows down the partial rewriting operation. Such liquid crystal materials having a slow response rate include SCE-8 manufactured by BDH Co. as used in an article "The JORES/ALVEY Ferroelectric Multiplexing Scheme published by RSRE at the FLC'91 Society. Since SCE-8 has a memory pulse width ta of about 70 .mu.s at a voltage as shown in FIG. 11 of 3Va/2=30 V, it takes time T.sub.p as shown in the following equation as time required for partial scanning when the number of scanning electrodes to be driven for partial rewriting operation: EQU T.sub.p =70.mu.s.times.6.times.200.times.(3/2)=126 ms
In addition, an increase in the number of scanning electrodes to be driven for partial rewriting operation will results in the prolonged time T.sub.p required for partial rewriting operation, thereby making it impossible for a displayed screen to track an image to be displayed.